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YAMAR
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Preliminary Data Sheet
SIG61 - Smart Slave for DC-BUS Powerline Network
This information is preliminary and may be changed without notice
1 GENERAL
The SIG61 is an independent slave in a DC-BUS Powerline communication network controlled by a SIG60 master device. The SIG61 has 4 identification (ID) pins, used to set the device address, 8 input pins and 8 output pins. The master can access any SIG61 device independently by using the proper device address. Data received from a remote SIG60 Master device is reflected to its output pins. The Master device can read the SIG61 input pins remotely. Its small footprint integrates most of the components needed for proper operation allowing small-size control solutions. The SIG61 is an economical slave device for applications such as controlling motors, reading sensors etc., eliminating the need for dedicated control wires and a host controller for its operation. It helps reducing the harness size and increase reliability. The SIG61 has a sleep mode that enables power saving; special Wakeup messages on the DC line are used to signal the sleeping devices to return to normal operation mode. The SIG61 is useful for a wide range of Automotive, Avionics and Industrial applications such as sensor reading, actuator activation, doors, seats, mirrors, climate control, lights, Truck-Trailer, etc. Host Master
8 ID 4 8 8 ID 4 8
SIG61
SIG61
Battery Power Line Figure 1.1 - SIG61 Application example
Applications
* * * * * * * * Truck-Trailer sub-bus Door module Climate control network Front and back Lights Sensors Actuators network Entertainment control Green Energy management Security Monitoring
Features
* * * * * * * * * 7 selectable Carrier frequencies 1.75MHz - 13MHz Selectable bit rate between 9.6 Kbps to 115.2 Kbps. 8 output and 8 input pins Eliminates data wires and transceiver. Operates over wide range of noisy power supply / battery lines. Byte oriented communication. Sleep Mode for low power consumption. Allows Master - Slave multiplex networks Several independent networks can operate over the same wire using different carrier frequencies. * Small footprint QFN 64 pin package
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2 OVERVIEW
The SIG61 is an independent slave in a Master-Slaves network operating on a selected narrow band channel. A single SIG60 master controls all the slaves in a network; the slaves may be SIG61 devices as well as SIG60 devices operating as slaves. Proper Network operation is maintained by employing 5 types of command messages: Read, Readchange, Write, Sleep and Change-Frequency. The command format is similar to the standard Universal Asynchronous Receiver Transmitter (UART). The SIG61 has internal narrow band modem, capable of operating in noisy environments. The receiver listens to the DC-BUS on its preset frequency. It filters out the signal from noise and interference and tries to recover the original command. If the checksum is correct, the SIG61 extracts the ID, Command and the Data. If the received ID matches its own ID, the SIG61 proceeds to detect the received command. When a Write command is received, the data part of the command is directed to the corresponding 8 output pins. When a Read command is detected, the SIG61 responds by transmitting a dedicated message towards the master containing an image of its 8 input pins. Multiple networks can operate concurrently on the same wire using different carrier frequencies.
2.1
Channels and Network
The SIG60-SIG61 network supports 16 combinations of frequency pairs. When set to such a pair, it is easy to switch from one frequency to the other when such need arises. Each channel accommodates a single SIG60 master and up to 15 SIG61/SIG60 slave devices. Additional SIG60-SIG61 networks can coexist on the same power line by employing different frequencies for each network, thus allowing different applications. Channel frequencies: 1.75MHz, 4.5MHz, 5.5MHz, 6.0MHz, 6.5MHz, 10.5MHz and 13.0MHz. Data transfer rate: 9.6Kbps up to 115.2Kbps. Cable length: Dependant on external AC loads connected to the DC line.
2.2
The SIG61 Device
Figure 2.1 outlines the building blocks of the SIG61 device.
Figure 2.1 - SIG61 Logical Blocks
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3 SIG61 SIGNALS
Device signals are described in table 3.1.
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 INH nSleep AutoSleep nReset Out0 Out1 Wake Out2 Out3 MF1nF0 Out4 Out5 TxOn Out6 Out7 RxOn
F0F1-0 F0F1-1 Gnd OscO OscIn AGnd F0F1-2 F0F1-3 Vcc F1B F0B AVdd RxP Mode3 Mode4 AutoFreqCh
Gnd Vdd HDO In7 In6 F1nF0 In5 In4 In3_HDC In2_HDI Vdd In1 DTxO Gnd In0 Mode2_LBD
SIG61
Id0 Test Id1 Id2 Id3 Vdd RxIn RxN TxO Gnd Gnd NC Vdd InterHope BitRate1 BitRate0
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
EXP
EXP
Pin name HDO INH
Pin# Pin type 35 32 Output 8mA Output 8mA Input Input
nSleep Wake
31 26
Control Signals Digital data output signal. Output the received data from the powerline to the host. Inhibit output for enabling the host or an external voltage regulator powering the host. This signal is HIGH in the normal and standby modes and LOW in sleep mode. Sleep control input. Pulling this signal to LOW puts the SIG61 in sleep mode. Should be pulled to Vdd. Local wakeup input. Negative or positive edge triggered. This pin can be connected to an external switch in the application. When the pin is triggered the device will wake up and send a wake up message to all the devices on the network. When not in use, this pin should be pulled Up or Down. is detected on the DC line. When HIGH, detection of interference switches the operating frequency between F0 and F1. If at the new frequency, no reception occurred for 2 sec, the operating frequency is switched back. For designs with a single channel this pin should be tied to ground.
nReset InterfHop
29 3
Input, PU Reset Input Input, PD Allows automatic frequency hoping whenever an interference signal
Test MF1nF0
15 23
OscO
52
Input, PD Should be connected to Gnd Output Output indicating the operating frequency. F1 when HIGH and F0 12mA when LOW. Line Interface signals Analog Crystal Output Output
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49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Figure 3.1 - SIG61 Pin-out
Description
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OscIn RxN RxP DTxO RxIn TxO F0B F1B TxOn RxOn In0 In1 In2_HDI In3_HDC In4 In5 In6 In7 Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7
53 9 61 45 10 8 59 58 20 17 47 44 42 41 40 39 37 36 28 27 25 24 22 21 19 18
Analog Input Analog Output Analog Input Tristate/ Output 2mA Analog Input Analog Output Analog, Bi directional Analog, Bi directional Output 12mA Output 12mA
Crystal Input
The internal comparator negative pin. Its value is internally pulled to Vdd/2. Bypass RxN to Ground with a 1nF capacitor. Positive pin input signal. Should be tied to RxN with a 1K Ohm resistor. Modulated digital transmit signal output to both ceramic filters.
Receive input from the DC-BUS to the RX operational amplifier. This
input is pulled internally to Vdd/2.
Transmit output.
F0 External filter I/O. Its value is internally pulled to Vdd/2. F1 External filter I/O. Its value is internally pulled to Vdd/2. HIGH when the device is transmitting a message. HIGH when the device is in receive mode.
I/O Signals Input PD The pin is read by the Master with a Read or Read-Change
command.
Input PD The pin is read by the Master with a Read or Read-Change Input Input Input PD Input PD Input PD Input PD Output 8mA Output 8mA Output 8mA Output 8mA Output 8mA Output 8mA Output 8mA Output 8mA Input PD Input PD Input PD Input PD
command. The pin is read by the Master with a Read or Read-Change command. When in SIG60 mode, HDI input. The pin is read by the Master with a Read or Read-Change command. When in SIG60 mode, HDC input. The pin is read by the Master with a Read or Read-Change command. The pin is read by the Master with a Read or Read-Change command. The pin is read by the Master with a Read or Read-Change command. The pin is read by the Master with a Read or Read-Change command. Output of data bit 0 when the Write command received from Master. Output of data bit 1 when the Write command received from Master. Output of data bit 2 when the Write command received from Master. Output of data bit 3 when the Write command received from Master. Output of data bit 4 when the Write command received from Master. Output of data bit 5 when the Write command received from Master. Output of data bit 6 when the Write command received from Master. Output of data bit 7 when the Write command received from Master.
Configuration Signals
Id0 Id1 Id2 Id3
16 14 13 12
SIG61 bit 0 ID address in the network. SIG61 bit 1 ID address in the network. SIG61 bit 2 ID address in the network. SIG61 bit 3 ID address in the network.
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F0F1-0 F0F1-1 F0F1-2 F0F1-3 BitRate0 BitRate1 NC Mode2 Mode3 Mode4 AutoFreqCh AutoSleep F1nF0 Gnd Vdd AGnd AVdd Exp
49 50 55 56 1 2 5 48 62 36 64
Should be left unconnected. Should be connected to Vdd. Should be connected to Vdd Automatic Frequency Change. When HIGH, the device automatically switches frequency after about 4 seconds without bus activity. 30 Input PD When this pin is set to HIGH, the device will automatically enter sleep mode after about 8 seconds without bus activity.
Input PD Input PD Input PD Input PD Input PD Input PD --Input PD Input PD Input PD Input PD
Frequency selection pins. See 4.2. Frequency selection pins. See 4.2. Frequency selection pins. See 4.2. Frequency selection pins. See 4.2. Bit rate selection pins. See 4.3. Bit rate selection pins. See 4.3. Not connected.
Input PD Selects between F0 / F1. HIGH - F1, LOW - F0 Power signals 4,11, Power Ground 34,43, 57 6,7,33, Power 3.3V power supply. 46,51 54 Power Analog Ground 60 Power 3.3V Analog Power. Separate from Vdd with a 10 Ohm resistor and bypass to Ground with 1nF and 10nF capacitor. Exp May be connected to GND
38
PD - Pull down resistor 100K ohm %30 PU - Pull up resistor 100K ohm %30
Table 3.1 - Device signals
3.1 Power Signals
Vdd and Gnd layout traces should be as wide as possible. It is recommended to connect a 0.1uF capacitor between each Vdd and ground pins, as close as possible to the pins. Analog Vdd pin, AVdd, should be connected to Vdd. AGnd should be connected to ground. The Analog supply has to be sufficiently powerful (capable of current driving), to avoid any fluctuations of supply voltage level. It is recommended to keep the lines connecting the 3.3V power supply to Vdd pins as short as possible with wide PCB traces.
AVdd Vdd R3 10 C5 1n C6 10n
Figure 3.2 - Recommended AVdd circuitry
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Outputs port J2 1 2 3 4 5 6 7 8 9 10 Vdd R5 R6 100K 100K AutoSleep Vdd R7 R10 R8 100K100K100K Inputs port 10 9 8 7 6 5 4 3 2 J1 1 Vdd 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 INH nSleep AutoSleep nReset Out0 Out1 Wake Out2 Out3 MF1nF0 Out4 Out5 TxOn Out6 Out7 RxOn 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
F1nF0
Vdd
R11 NC
F0F1-0 F0F1-1 Gnd OscO OscIn AGnd F0F1-2 F0F1-3 Vcc F1B F0B AVdd RxP Mode3 Mode4 AutoFreqCh
Gnd Vdd HDO In7 In6 F1nF0 In5 In4 In3_HDC In2_HDI Vdd In1 DTxO Gnd In0 Mode2_LBD
SIG61
Id0 Test Id1 Id2 Id3 Vdd RxIn RxN TxO Gnd Gnd NC Vdd InterHope BitRate1 BitRate0
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Id0 Id1 Id2 Id3 Vdd C10 100p D2 Vdd InterHope BitRate1 BitRate0 R16 680 BAS70-04 D1
C4 AC/DC BUS 560p/200V
C9 1n
BAS70-04
R1 1K
EXP
EXP
49 50 51 52 53 54 F0F1_2 55 F0F1_3 56 57 58 59 60 61 MODE3 62 MODE4 63 64 F0F1_0 F0F1_1
AutoFreqChange Vdd 3 R12 1K R2 1 SFE5.5 F1 1K C3 1n
C7 X1 1nF C1 4MHz *pF R3 *pF C8 Vdd 10 C5 1n C6 10n 1nF C2 VCC
3 R13 1K
1 SFE6.5 F0
Figure 3.3 - Typical SIG61 dual channel circuit Note: All the signals indicated in red, should be tied either to Gnd, or Vdd, according to the desired mode of operation.
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3.2 Ceramic Filter
The SIG61 can operate with a single ceramic filter for transmission and reception. If, however, switching between two channels is desired, two ceramic filters will be required. The minimum allowable 3dB bandwidth of the ceramic filters is 70 kHz. Choosing a narrower bandwidth shall limit the maximum achievable bit rate. The SIG61 selectable carrier frequencies are chosen in accordance with ceramic filter values available in the market. Nominal 3 dB BW 20dB Insertion Stop band In/Out freq. [KHz] BW loss attenuation imped. [MHz] [KHz] [dB] [] [dB]
*1.75 4.50 5.50 6.00 6.50 **10.50 70 80 80 80 150 750 750 750 800 6.0 6.0 6.0 6.0 4.5 30 30 30 30 1000 600 470 470 330
Murata part #
Discrete SFSL4.5MDB SFSL5.5MDB SFSL6.0MDB SFSL6.5MDB SFELF10M5JAA001-B0 Discrete filter for 115.2Kbps SFELK13M0JA00-B0 Discrete
Oscilent part #
773-0045 773-0055 773-0060 773-0065
**13.00 280 4.5 330 *1.75 * 1.75MHz can operate only at 9.6Kbps ** 10.5MHz and 13.00MHz can operate at 115.2Kbps instead of 9.6Kbps.
3.3
Oscillator
The SIG61 is designed to operate with a low cost 4MHz crystal connected between OscIn and OscOut pins. Each of these pins should be connected to the ground via a capacitor. All the corresponding PCB traces should be as short as possible. Recommended crystals are: 1. NDK AT-51 GW. 2. Epson MA-506. The values of C1, and C2 in Figure 3.3, pertaining to the oscillator circuitry, should be determined according to the crystal manufacturer recommendations. Values between 0pF and 4.7pF may serve as good starting point. The overall frequency tolerance should not exceed 200ppm.
3.4
Communication performance
The maximum cable length between two devices depends mainly on the AC impedance of loads connected to that line and number of nodes. The DC cable length has less effect on communication. The SIG61 requires a minimum received signal of 20mVpp for proper reception.
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4 4.1
DEVICE OPERATION Protocol
The following paragraph describes the operation of the SIG61 device.
The device operation is controlled via 5 types of commands: Write command - Upon receiving a Write command with the SIG61 specific ID, the device shall output the data byte content as indicated by the command to its Output pins. Read command - Upon receiving a Read massage with the SIG61 specific ID, the device shall respond by sending a message containing the status of its Input pins (followed by an appropriate checksum). Read-Change command - When receiving a Read-Change massage with the SIG61 specific ID, the device shall respond to the command by indicating if a pulse upon detecting the first change on its input pins. The response message shall contain the new status of the input pins followed by an appropriate checksum. Sleep command - Upon receiving a Sleep command, the device shall enter a low power-consumption (sleep) mode. A wakeup message generated by the master, or by any of the slaves, wakes up all the devices on the network. This is a global message targeting all the slaves in the network. Change-Frequency command - Upon receiving Change-Frequency command, the device shall switch from its current operational frequency to the other. This command is a global command targeting all the slaves in the network. 4.1.1 Command structure The structure of the five types of commands is detailed below.
Command type 1: Write command.
The Write command consists of 5 bytes: sync break, sync field, Identifier, data and checksum. The identifier byte begins with the device four ID bits, followed by 00 bits and 2 protection bits. Upon receiving a write command, if checksum and protection bits calculations are successful, the data byte content is transferred to the corresponding output pins. Sync break: Sync break length is at least 13 bit times with compliance to Lin protocol. Protection bits calculation: P0 = (Identifier [0]) XOR (Identifier [1]) XOR (Identifier [2]) XOR (Identifier [4]) P1 = ~ ((Identifier [1]) XOR (Identifier [3]) XOR (Identifier [4]) XOR (Identifier [5])) Checksum calculation: The checksum is an inverted 8 bit sum of the Identifier and Data byte including (own) carry: Checksum = ~ ( Identifier Byte + Data Byte + Carry)
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Transmitted command Sync break Sync Field P1, P0, 0, 1, Address Out [7:0] Checksum
3 bit delay
SIG61 Outputs at receiving device
Figure 4.1 - Write command
Command type 2: Read command.
The Read command, initiated by the Master, requests the status of the SIG61 input pins. The Read command from the master consists of 3 bytes: sync break, sync field and identifier. The identifier of this command begins with the four-bit ID of the device, followed by "01", and finally 2 protection bits. The two protection bits are calculated as described above. If header detection is correct (including protection bits), the SIG61 device (whose ID matches the one in the command) shall respond by sending two bytes. A data byte containing the status of its eight input Signal pins followed by a checksum byte. The checksum calculation is carried out as in the description above while part of it, the identifier byte, was transmitted by the Master. Figure 4.2 shows a generic Read command.
Sync break Sync Field P1, P0, 0, 0, Address Data (8 input bits) Checksum
Master
Slave
Figure 4.2 - Read command
Command type 3: Read-change
The Read-change command is similar to the Read command. However, it enables to detect any change in the input pins (pulse-like behavior) that may have occurred between two consecutive Read or Readchange commands. The command from the master instructs the SIG61 to send back information on changes of its input pins since the last Read or Read-change command. The first change on the pin after the Read command sets its bit value. Figure 4.3 shows the process of determining the sent bit value of an input pin. "1" "1" "0" "0"
Sent value
Change
Input pin level Read -change command
1 bit
Figure 4.3 - Determining the recent changed value of an input pin The Read-change command from the master has 3 bytes: sync break, sync field and identifier. The identifier begins with the destination device four-bit ID, followed by 10 and terminating with 2 protection bits. The response for this command is a data byte containing the SIG61s input pins recent changed value, followed by the checksum byte. See checksum and protection bits calculation description above. Figure 4.4 shows a Read-changes command.
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Sync break
Sync Field
P1, P0, 1, 0, Address
Data (8 input bits)
Checksum
Master Figure 4.4 - Read-change command
Slave
Command type 4: Sleep command.
This type of command consist of 5 bytes: sync break, sync field, "3C" Hex, "00" Hex and checksum. The sleep command identifier is "3C"Hex as in LIN2.0 specifications and the following data byte "00"Hex. Upon reception of sync break, sync field, "3C"Hex and "00"Hex bytes, a device enters sleep mode immediately and as a result it's the following command bytes are ignored.
Sync break
Sync Field
0x3C
Zero byte/bytes
Checksum
Figure 4.5 - Sleep command
Command type 5: Change Frequency command.
This type of command consists of 5 bytes - sync break, sync field, "FE" Hex, "00" Hex and checksum. The change frequency command identifier is "FE" Hex and the following data byte is "00"Hex. Upon reception of sync break, sync field, "FE" Hex and "00" Hex bytes the frequency changes from F1 to F0, or vise versa. Checksum calculation follows the description above.
Sync break
Sync Field
0xFE
Zero byte/bytes
Checksum
Figure 4.6 - Frequency Change command
4.2
Power Management
The SIG61 device features Sleep mode for power saving. Entering the Sleep mode, as well as waking up, can be initiated locally, by means of dedicated input pins, or remotely through activity (proper messages) over the bus. 4.2.1 Entering Sleep mode The SIG61 can enter sleep mode by any of the following ways: 1. The device nSleep pin is lowered. 2. Sleep command from a remote master is received. 3. The AutoSleep pin is set HIGH and no reception occurred for about 8 seconds. 4.2.2 Device Outputs during Sleep During Sleep mode, the SIG61 8 output pins remain unchanged if the device has entered this mode due to a Sleep command from the Master or by lowering the Pin nSleep. However if the device entered the Sleep mode due to the AutoSleep function, SIG61 will lower all the outputs to "0".
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4.2.3 Remote wake up process The SIG61 can be awakened by a remote SIG60 master, or SIG61 slave, device transmitting a wakeup message over the bus. During Sleep Mode, the SIG61 wakes up periodically, every 32mSec, to sense for bus activity. If a wakeup message is detected, the SIG61 device raises pin INH and lowers pin HDO. If nSleep pin is low upon remote waking up, the local host (a device controlling the SIG61) which initially pulled nSleep pin down, must raise the nSleep back high. Figure 4.7 provides the signal description. Wakeup Message DC-BUS INH HDO
Standby Normal mode msg. detected
Figure 4.7 - Wakeup from bus message 4.2.4 Wakeup from Wake pin A transition seen on the Wake pin (caused by an external source) is used to wake up the device. The device then enters Standby mode, it rises pin INH, and transmits a wakeup message to the bus. While transmitting the wakeup message, the device lowers pin HDO. After the transmission is completed the device raises pin HDO. This is depicted in Figure 4.8. After the transmission is completed the device enters Normal mode. If nSleep pin is low upon waking up, the local host which initially pulled nSleep pin down, must raise the nSleep back to high. Wake INH DC-BUS HDO
Normal
T1 Wakeup Message
Standby
T1 = 30uS-62uS T2 = 92uS-124uS
T2
mode
Figure 4.8 - Wakeup from Wake pin
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4.3
SIG61 Configuration
The Pins labeled "Mode 4" and "Mode 3" should be tied up to Vdd. The SIG61 operates at default with the following parameters: Bit rate: 19.2Kbps, F0=5.5MHz, F1=6.5MHz The following configuration bits set the operating frequencies according to table 4.2. Table 4.2 - F0, F1 select F0F1 (3:0) pins F0 F1 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1.75Mhz 1.75Mhz 1.75Mhz 1.75Mhz 4.5Mhz 4.5Mhz 4.5Mhz 4.5Mhz 10.5Mhz 5.5Mhz 5.5Mhz 6.0Mhz 6.0Mhz 6.5Mhz 6.5Mhz 5.5Mhz 4.5Mhz 5.5Mhz 6Mhz 6.5Mhz 5.5Mhz 6.0Mhz 6.5Mhz 10.5Mhz 13.0Mhz 10.5Mhz 13.0Mhz 10.5Mhz 13.0Mhz 10.5Mhz 13.0Mhz 6.5Mhz 00 19.2K 19.2K 19.2K 19.2K 19.2K 19.2K 19.2K
Table 4.3 - bit rates selection 11 10 01 BitRate (1,0) Pins Frequency 1.75 MHz 9.6K 4.50 MHz 38.4K 57.6K 9.6K 5.50 MHz 38.4K 57.6K 9.6K 6.00 MHz 38.4K 57.6K 9.6K 6.50 MHz 38.4K 57.6K 9.6K 10.50 MHz 38.4K 57.6K 115.2 13.00 MHz 38.4K 57.6K 115.2 Signal AutoSleep ID[3:0] F1nF0 InterHop High ("1") Auto Sleep On Defines device ID Select F1 InterHop On
Low ("0") Auto Sleep Off Select F0 InterHop Off
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5 5.1
ELECTRICAL PARAMETERS Absolute Maximum Rating
-40C to 125C -55C to 150C -0.6V to Vdd+0.3V -0.3V to 4V
Ambient Temperature under bias Storage Temperature Input Voltage Vdd Supply voltage
5.2
Electrical Operating Conditions
Characteristics Supply Voltage Supply Current Supply Current during Tx Supply Current in Sleep mode Min 3.0 Typ 3.3 40 50 80 Max 3.6 Units V mA mA uA Conditions 5.5MHz 5.5MHz
Symbol Vdd Idd Idd Ipd
5.3
Symbol VIH VIL VOH VOL Iout IIN
DC Electrical Characteristics
Characteristics Minimum high level input voltage Maximum low level input voltage Minimum high level output voltage Maximum low level output voltage Maximum output current, other pins Maximum input current Vdd 3.0 3.0 3.0 3.0 Typ 2.1 0.9 2.4 0.4 Units V V V V Conditions
See pins table 3.3 10 uA
5.4
Operating Temperature
0C to 70C -40C to 85C
Commercial: Industrial:
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5.5
Mechanical Information
Package type - QFN 64 pin
Figure 5.1 - QFN64 mechanical dimensions
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DS-SIG61 R0.932
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Revision changes: Revision 0.2 0.4 0.5 0.61 0.7 0.8 0.9 0.92 0.93 Date 2.3.2008 22.5.2009 25.5.2009 22.7.2009 13.9.2009 20.11.2009 20.12.2009 28.12.2009 7.1.2010 Comments Detailed description Updated schematic Updated pin information Updated mechanical drawing Added "Outputs during Sleep" Added checksum and parity calculations Renumbering figures Update the Write and Read commands. Update tables 4.2- 4.3 Added 3.4.8 and 3.4.9 Updated schematics, protection network, Electrical parameters, pin description table Updated drawings, notations, descriptions. Updated Read-change command explanation
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